Several conflicting objectives are present in the field of high performance data acquisition for electrical power measurement, metering, and management. A first objective is high data resolution. The availability of high resolution analog-to-digital conversion methods, such as with sigma-delta modulators, combined with the power of state of the art digital signal processors provides the capability to achieve significant levels of accuracy. Thus, complex signal processing may be performed on precise data using conventional signal processing architectures. However, a second objective is increased signal processing bandwidth. An inherent tension exists between these two objectives in that increasing bandwidth typically occurs at the expense of data resolution. Yet, a third objective is compactly integrated or electronic circuitry that requires less power to operate. A need thus exists for a decimation filter having the capability to balance high data resolution demands against large bandwidth demands, as desired for power measurement, metering, and management systems, while having the size and power requirements of a conventional electronic or integrated circuit component.
It is further desirable to provide a decimation filter with improved normalization or scaling characteristics in order to improve data access speed and minimize filter circuitry complexity. U.S. patent application Ser. No. 08/025,456 by J. E. Krisciunas et al, filed Mar. 3, 1993, assigned to the assignee of the present application and herein incorporated by reference, describes a technique which, although effective in providing suitable normalization for a desired decimation ratio, employs relatively complex synchronous conversion on the filter output signals. The technique described therein uses a parallel-to-serial (PISO) converter and/or tapped delays which, in general, are not suitable for asynchronously reading out filter output signals for any additional signal processing. The present invention advantageously provides a coefficient generator having the capability of providing coefficient signals with variable scaling. U.S. patent application Ser. No. 08/265,475, by D. A. Staver et al, filed concurrently herewith and herein incorporated by reference, describes a coefficient generator which, although capable of efficiently providing coefficient signals with variable scaling, employs circuitry which somewhat may not be as readily expandable as the coefficient generator of the present invention. In accordance with another objective of the present invention, an overflow detector is employed in the decimation filter to detect and correct any overflow condition which can occur under predetermined conditions. As described in U.S. patent application Ser. No. 08/025,456 by J. E. Krisciunas et al, one way to avoid the overflow condition is to modify the ideal response of the filter. In general, this modification results in a slight alteration in the magnitude response of the decimation filter realization which can introduce substantial distortion at relatively low decimation ratios. Thus, there is a need to provide a decimation filter in which the magnitude response is impervious to any selected decimation ratio.